1. Field of the Invention
The present invention relates to semiconductor integrated circuits and, in particular, to a TTL-compatible, high-speed output buffer that has a switching delay substantially independent of output loading over a specified loading range and that provides controlled output edge rates that are substantially independent of loading, temperature, supply voltage and edge transition.
2. Description of the Related Art
An output buffer is a circuit which may serve a number of functions. First, output buffers are frequently required to translate an input family of voltages levels to a different output family of voltage levels. Output buffers are also often required to generate TTL compatible output signals even though the output buffer is internally designed with emitter coupled logic. Additionally, output buffers are commonly required to drive heavily capacitively loaded signal and bus lines on a printed circuit board through large voltage swings.
Output buffers which are utilized in complex high speed digital systems are often required to possess not only voltage translation and capacitive drive properties, but are also required to meet tight timing constraints. These timing constraints can include 1) a constant buffer delay which is independent of the output loading, changes in the surrounding temperature, the power supply voltage, and the transition polarity and 2) output edges which exhibit controlled ramp rate characteristics.
The tight timing constraints are especially important when an output buffer is used as an output clock driver buffer. An output clock driver buffer provides critical system clock signals to other integrated circuits on the printed circuit board and may also be fed back into the integrated circuit from which it was generated.
An output clock driver buffer may have multiple drivers wherein each driver drives a clock signal which is phase offset from the other clock signals. Even when each driver has a different output loading, each driver must still meet the critical timing relationships between the different clock signals.
Thus, there is a need for an output buffer which has a fixed delay independent of its loading over temperature and power supply ranges. Since the time required for the output to transition from either high or low or low to high is the major portion of the buffer delay, a buffer which exhibits a controlled output slew rate over variations in loading, temperature, VCC voltage, transition polarity, will be able to meet this critical timing requirement.
In addition to being able to meet critical timing requirements, another advantage to controlled output slew rate is that it can be set to a value which will lead to a minimum of overshooting and undershooting on the output waveform. Buffers with uncontrolled fast edges can, when used in an environment with inductive leads, cause ringing on the output signals, which can cause timing errors in circuits fed by the output. It would, therefore, be desirable to have available an output buffer that provides controllable, smooth output transitions independent of loading, temperature, and polarity of transition.